1. Field of the Invention
The present invention generally relates to a semiconductor device and a method of forming the same.
Priority is claimed on Japanese Patent Application No. 2006-313179, filed Nov. 20, 2006, the content of which is incorporated herein by reference.
2. Description of the Related Art
All patents, patent applications, patent publications, scientific articles, and the like, which will hereinafter be cited or identified in the present application, will hereby be incorporated by reference in their entirety in order to describe more fully the state of the art to which the present invention pertains.
In recent years, computers or electric devices include one or more large scale integrated circuits, hereinafter referred to as LSI, in which a large number of MOS transistors and resistances may typically be integrated on a single chip. Dynamic random access memories (DRAMs) include LSIs. The DRAM needs shrinkage of LSI. Shrinkage of the LSI may cause remarkable short channel effects of the MOS transistors integrated in the LSI, even the short channel effects are desired to be suppressed.
Japanese Unexamined Patent Application, First Publication, No. 2005-251776 discloses a conventional technique for suppressing the short channel effects of the MOS transistor. In accordance with the conventional technique, epitaxial silicon layers are electively formed by a selective epitaxial growth over source and drain regions of a substrate. The epitaxial silicon layers are used as source and drain regions of the MOS transistor. Increasing the thickness of the epitaxial silicon layers enhances the suppression of the short channel effects of the MOS transistor.
The shrinking DRAM cell size, particularly 6F2 cell, needs a narrow pitch field pattern. As described above, the epitaxial silicon layers act as the source and drain regions of the MOS transistors in the memory cells. In the selective epitaxial growth, the epitaxial silicon layers are grown not only in the thickness direction but also in the lateral direction perpendicular to the thickness direction. Increasing the thickness of the epitaxial silicon layers increases the growth in the lateral direction of the epitaxial silicon layers. If the pitch of the field pattern is very narrow, increasing the thickness of the epitaxial silicon layers narrows a gap between the epitaxial silicon layers. In some cases, the thickness of the epitaxial silicon layers may form a short circuit between the epitaxial silicon layers.
The MOS transistors are further used in peripheral circuits of the DRAM. Shrinkage of the DRAM needs shrinkage of the peripheral circuits. Shrinkage of the peripheral circuits may reduce contact areas between the source and drain diffusion regions and contact plugs. Reduction in the between the source and drain diffusion regions and contact plugs increases contact resistances between the source and drain diffusion regions and contact plugs, even the contact resistances are desired to be low.
A known conventional technique for reducing the contact resistances of the MOS transistors in the peripheral circuits is to carry out an ion-implantation at a high impurity concentration for implanting ions into epitaxial silicon layers, parts of which are adjacent to contact holes, in which the contact plugs are formed, wherein the epitaxial silicon layers are disposed over the source and drain regions of a substrate.
In order to avoid the above-described problems, it is necessary that the epitaxial silicon layer is not thick. Ion-implantation for introducing ions into the non-thick epitaxial silicon layers at a high concentration may enhance the short channel effects of the MOS transistor. Namely, carrying out the ion-implantation for introducing ions into non-thick epitaxial silicon layers at a high concentration may cause that the ions will be diffused by a subsequent diffusion process into the source and drain diffusion regions that are disposed under the epitaxial silicon layers. As a result, the impurity concentration of the source and drain diffusion regions unintentionally increased, thereby enhancing the short channel effects.
In view of the above, it will be apparent to those skilled in the art from this disclosure that there exists a need for a semiconductor device and a method of forming the same. This invention addresses this need in the art as well as other needs, which will become apparent to those skilled in the art from this disclosure.